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fractional - n frequency synthesizer data sheet adf4154 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog dev ices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of an alog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 2012 analog devices, inc. all rights reserved. features rf bandwidth to 4 ghz 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage programmable dual - modulus prescaler 4/5, 8/9 programmable charge pump currents 3 - wire serial interface digital lock detect power - down mode pin compatible with the adf4110 / adf4111 / adf4112 / adf4113 , adf4106 , adf4153 programmable modulus on fractional - n synthesizer trade - off noise vs . spurious performance fast - lock mode with built - in timer loop filter design possible with adi s impll ? applications base stations for mobile radio (wimax, phs, gsm, pcs, dcs, cdma, pmr, w - cdma, s uper c ell 3g) wireless handsets (pmr, gsm, pcs, dcs, cdma, wcdma) catv equipment wireless lans communications test equipment general description the adf4154 is a fractional - n fr equency synthesizer that implements local oscillators in the up conversion and down conversion sections of wireless receivers and transmitters. it consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a - based fractional interpolator to allow programmable fractional - n division. the int, frac, and mod registers define an overall n - divider ( n = ( int + ( frac / mod ))). in addition, the 4 - bit reference counter (r - counter) allows selectable ref in frequencies a t the pfd input. a complete phase - locked loop (pll) can be implemented if the synthesizer is used with an ext ernal loop filter and a voltage - controlled oscillator (vco). a key feature of the adf4154 is the fast - lock mode with a built - in timer. the user can program a predetermined countdown time value so that the pll remain s in wide bandwidth mode, instead of the user having to control this time externally. control of all on - chip registers is via a simple 3 - wire interface. the device operates with a power su pply ranging from 2.7 v to 3.3 v and can be powered down when not in use. functional block dia gram lock detect fast-lock switch n counter cp rfcp3 rfcp2 rfcp1 reference data le 24-bit data register clock ref in av dd agnd v dd v dd dgnd r div n div dgnd cpgnd dv dd v p sdv dd r set rf in a rf in b output mux muxout ? + high z phase frequency detector adf4154 third order fractional interpolator modulus reg fraction reg integer reg current setting 2 doubler 4-bit r counter charge pump 04833-001 figure 1 .
adf4154 data sheet rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and pin function descriptions ...................... 6 typical performance characteristics ............................................. 7 circuit description ........................................................................... 9 referenc e input section ............................................................... 9 rf input stage ............................................................................... 9 rf int divider ............................................................................. 9 int, frac, m od, and r relationship ..................................... 9 r - counter ...................................................................................... 9 phase frequency detector (pfd) and charge pump .............. 9 muxout and lock detect ...................................................... 10 input shift registers ................................................................... 10 program modes .......................................................................... 10 registers ........................................................................................... 11 register definitions ................................................................... 16 r - divider register, r1 ............................................................... 16 control register, r2 ................................................................... 16 noise and spur register, r3 ...................................................... 17 reserved bits ............................................................................... 17 initialization sequence .............................................................. 18 rf synthesizer: a worked example ........................................ 18 modulus ....................................................................................... 18 reference doubler and reference divider ............................. 18 12- bit programmable modulus ................................................ 18 spurious op timization and fast lock ..................................... 18 fast - lock timer and register sequences ............................... 19 fast lock: an example .............................................................. 19 fast lock: loop filter topology ............................................... 19 spur mechanisms ....................................................................... 19 spur consistency ........................................................................ 20 filter design adisimpll ....................................................... 20 interfacing ................................................................................... 20 pcb design guidelines for chip scale package .................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 8 /12 rev. b to rev. c changes to figure 4 .......................................................................... 6 updated outline dimensions (changed cp - 20- 1 t o cp - 20 - 6) .... 22 changes to ordering guide .......................................................... 22 9/ 11 rev. a to rev. b changes to noise characteristics parameter ................................ 3 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 12 /06 rev. 0 to rev. a changes to features .......................................................................... 1 changes to applications .................................................................. 1 changes to functional block diagram .......................................... 1 changes to specifications ................................................................ 3 changes to absolute maximum ratings ....................................... 5 changes to typical performance characteristics conditions .... 7 replaced figure 5 through figure 7 ............................................... 7 changes to fig ure 13 ......................................................................... 8 changes to r - divider register map ............................................ 13 changes to control register map ................................................ 14 change to ref in doubler section ................................................ 18 added initialization sequence section ........................................ 18 change to 12 - bit programmable modulus section ................... 18 changes to fast - lock timer and register sequences section ........ 19 changes to fast lock: loop filter topology section ................ 19 deleted spurious signal section ................................................... 18 added spur mechanisms section ................................................ 19 added spur consistency section ................................................. 20 change to filter design adisimpll section .......................... 20 change to interfacing section ...................................................... 20 updated out line dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 5/ 04 revision 0: initial version
data sheet adf4154 rev. c | page 3 of 24 specifications av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ? . the operating te mperature for the b version is ? 40c to +80c. table 1. parameter b version unit test conditions/comments rf characteristics (3 v) see figure 15 for the input circuit. rf input frequency (rf in ) 1 0.5 /4.0 ghz min/max ? 8 dbm/0 dbm min/max. for lower frequencies, ensure slew rate > 400 v/s. 1.0/4.0 ghz min/max ? 10 dbm/0 dbm min/max. reference characteristics see figure 14 for input circuit. ref in input frequency 1 10/250 mhz min/max for f < 10 mhz, use a dc - coupled, cmos - compatible square wave, slew rate > 25 v/s. ref in input sensitivity 0.7/ av dd v p - p min/max biased at av dd /2 . 2 ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 3 32 mhz max charge pump i cp sink/source programmable. see table 5 . high value 5 ma typ with r set = 5.1 k?. low value 312.5 a typ absolute accuracy 2.5 % typ with r set = 5.1 k?. r set range 2.7/10 k? min/max i cp three - state leakage current 1 na typ sink and source current. matching 2 % typ 0.5 v < v cp < v p ? 0.5 v . i cp vs. v cp 2 % typ 0.5 v < v cp < v p ? 0.5 v . i cp vs. temperature 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 1.4 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage 1.4 v min open - drain 1 k? pull - up to 1.8 v. v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 2.7/3.3 v min/v max dv dd , sdv dd av dd v p av dd /5.5 v min/v max i dd 24 ma max 20 ma typical. low power sleep mode 1 a typ noise characteristics normalized phase noise f loor (pn synth ) 4 ? 220 dbc/hz typ pll loop bw = 500 khz . measured at 100 khz offset. normalized 1/f noise (pn 1_f ) 5 ?114 dbc/hz typ 10 khz offset; normalized to 1ghz. phase noise performance 6 @ vco outpu t. 1750 mhz output 7 ? 102 dbc/hz typ @ 1 khz offset, 26 mhz pfd frequency. 1 use a square wave for frequencies below f min . 2 ac coupling ensures av dd /2 bias. see figure 14 for a typical circuit. 3 guaranteed by design. sample tested to ensure compliance. 4 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the output of the vco and subtracting 20 log(n) (where n is the n divider value) and 10 log(f pfd ). pn synth = pn tot ? 10 log(f pfd ) ? 20 log(n). 5 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1 /f noise contribution at an rf frequency, f rf , and at a frequency offset f is given by pn = p n 1_f + 10 log(10 khz/f) + 20 log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll. 6 the phase noise is measured with the eval - adf4154 eb1 an d the hp8562e spectrum analyzer. 7 f r efin = 26 mhz, f pfd = 26 mhz, offset frequ ency = 1 khz, rf out = 1750 mhz, loop b/w = 20 khz, lowest noise mode.
adf4154 data sheet rev. c | page 4 of 24 timing characteristi cs av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ?. table 2. parameter 1 limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock l ow duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width 1 guaranteed by design, but not production tested. clock dat a le le db23 (msb) db22 db2 db1 (contro l bit c2) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04833-026 figure 2 . timing diagram
data sheet adf4154 rev. c | page 5 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter 1 , 2 , 3 rating v d d to gnd ? 0.3 v to +4 v v dd to v dd ? 0.3 v to +0.3 v v p to gnd ? 0.3 v to +5.8 v v p to v dd ? 0.3 v to +5.8 v digital i/o voltage to gnd ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd ? 0.3 v to v dd + 0.3 v ref in , rf in to gnd ? 0.3 v to v dd + 0.3 v opera ting temperature range industrial (b version) ? 40c to +85c storage temperature range ? 65c to +150c maximum junction temperature 150c tssop ja thermal impedance 112c/w lfcsp ja thermal impedance (paddle soldered) 30.4c/w reflow soldering peak temperature 260c time at peak temperature 40 sec 1 this device is a high performance rf - integrated circuit with an esd rating of <2 kv, and it is esd sensitive. pr oper precautions should be taken when handling and assembling the device. 2 gnd = a gnd = d gnd = 0 v. 3 v dd = av dd = dv dd = sdv dd . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adf4154 data sheet rev. c | page 6 of 24 pin configuration and pi n function descriptions adf4154 top view (not to scale) agnd 4 rf in b 5 rf in a 6 av dd 7 ref in 8 le data clk sdv dd dgnd 13 12 11 10 r set 1 cp 2 cpgnd 3 v p dv dd muxout 16 15 14 9 04833-002 figure 3. tssop pin configuration 04833-003 14 13 12 1 3 4 le 15 muxout data clk 11 sdv dd cpgnd agnd 2 agnd rf in b 5 rf in a 7 a v d d 6 a v d d 8 r e f i n 9 d g n d 1 0 d g n d 1 9 r s e t 2 0 c p 1 8 v p 1 7 d v d d 1 6 d v d d adf4154 top view (not to scale) notes 1. the exposed pad must be connected to agnd. figure 4. lfcsp pin configuration table 4. pin function descriptions tssop lfcsp mnemonic description 1 19 r set set resistor. connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is set cpmax r i 5.25 ? where r set = 5.1 k and i cpma x = 5 ma. 2 20 cp charge pump output. when enabled, this pin provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is th e ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf (see figure 15). 6 5 rf in a input to the rf prescaler. this small-signal input is normally ac-coupled from the vco. 7 6, 7 av dd positive power supply for the rf section. decoupling ca pacitors to the digital ground plane should be placed as close as possible to this pin. av dd has a value of 3 v 10%. av dd must have the same voltage as dv dd . 8 8 ref in reference input. this cmos input has a nominal threshold of v dd /2 and an equivalent input resistance of 100 k (see figure 14). this input can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 sdv dd -? power. decoupling capacitors to the digital grou nd plane should be placed as close as possible to this pin. sdv dd has a value of 3 v 10%. sdv dd must have the same voltage as dv dd . 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the shift register on the clk rising edge . this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two ls bs as the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le is high, the data stor ed in the shift registers is loaded into one of the four latches, which is selected by the user via the control bits. 14 15 muxout multiplexer output. this pin allows either the rf lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd positive power supply for the digital section. decoup ling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd has a value of 3 v 10%. dv dd must have the same voltage as av dd . 16 18 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. n/a ep epad exposed pad. the exposed pad must be connected to agnd.
data sheet adf4154 rev. c | page 7 of 24 typical performance characterist ics loop bandwidth = 20 khz ; reference = 250 mhz ; vc o = var i - l company, inc., vco190 - 1750t ; evaluation board = eval - adf4154eb1 ; measurements taken with the agilent e5500 phase noise measurement system. 04833-004 phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ?1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 20khz loo p b w , low noise mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.23 rms sirenz a 1750t vco 1k 10k 1m 10m 100m 100k frequency (hz) figure 5 . single - sideband phase noise plot (lowest noise mode) phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ?1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 1k 10k 1m 10m 100m 100k 04833-005 frequency (hz) 20khz loo p b w , low noise and spur mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.33 rms sirenz a 1750t vco figure 6 . single - sideband phase noise plot (low noise mode and spur mode) 04833-006 phase noise (dbc/hz) ?30 ?60 ?80 ?140 ?130 ?120 ?1 10 ?150 ?160 ?170 ?90 ?100 ?70 ?50 ?40 1k 10k 1m 10m 100m 100k frequency (hz) 20khz loo p b w , low spur mode rf = 1.7202mhz, pfd = 25mhz, n = 68, frac = 101, mod = 125, i cp = 625a, dsb integr a ted phase error = 0.36 rms sirenz a 1750t vco figure 7 . single - sideband phase noise plot (lowest spur mode) phase noise (dbc/hz) phase detec t or frequenc y (khz) ?130 ?140 ?150 ?160 ?170 100 1000 10000 100000 04833-010 figure 8 . pfd noise floor vs. pfd frequency (lowest noise mode) frequenc y (ghz) amplitude (dbm) 5 0 ?5 ?10 ?20 ?15 ?25 ?30 ?35 0 0.5 1.0 1.5 4.0 3.5 3.0 2.5 2.0 4.5 p = 4/5 p = 8/9 04833-0 1 1 figure 9 . rf input sensitivity v cp (v) 6 0 ?6 i cp (ma) 4 2 ?2 ?4 ?5 ?3 ?1 1 3 5 0 1 2 3 4 5 04833-012 figure 10 . charge pump output characteristics
adf4154 data sheet rev. c | page 8 of 24 r set v alue (k?) ?80 ?85 ?110 0 35 30 25 20 15 10 5 phase noise (dbc/hz) ?90 ?95 ?105 ?100 04833-013 figure 11 . phase noise vs. r set temperature (c) ?90 ?94 ?104 ?60 100 ?40 phase noise (dbc/hz) ?20 0 20 40 60 ?96 ?98 ?92 ?102 ?100 80 04833-014 figure 12 . phase noise vs. temperature 04833-028 time (s) 1 10 0 10 20 30 40 50 60 70 80 90 100 frequenc y (ghz) 1.700 1.696 1.692 1.688 1.684 1.680 1.676 1.672 1.668 1.664 1.660 1.656 1.652 1.648 1.644 1.640 lock time in fast-lock mode (fast counter = 150) lock time in normal mode low spur mode: 1649.7mhz to 1686.8mhz final loop bandwidth = 60khz figure 13 . frequency vs. lock time
data sheet adf4154 rev. c | page 9 of 24 circuit description reference input sect ion the reference input stage is shown in fi gure 14 . while the device is operating, usually sw1 and sw2 are closed switches and sw3 is open. when a power - down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that the ref in pin is not loaded while the device is powered down. buffer t o r counter ref in 100k? nc sw2 sw3 no nc sw1 power-down contro l 04833-027 fi gure 14 . reference input stage rf input stage the rf input stage is shown in figure 15 . it is followed by a two - stage limiting amplifier to generate the current mode logic (cml) clock levels needed for t he prescaler. bias generator 1.6v agnd a v dd 2k? 2k? rf in b rf in a 04833-015 figure 15 . rf input stage rf int divider the rf int cmos counter allows a division ratio in the pll feedback counter. division ratios from 31 to 511 are allowed. third order fractional interpolator frac v alue mod reg int reg rf n-divider n = int + frac/mod from rf input stage t o pfd n counter 04833-016 figure 16 . a and b counter s int, frac, mod, and r relationship the int, frac, and mod values, in conjunction with the r - counter, enable generating output frequencies that are spaced by fractions of the pfd . see the rf synthesizer: a worked example sec tion for more information. the rf vco frequency (rf out ) equation is ( ) ( ) mod frac int f rf pfd out + = (1) where rf out is the output frequency of the external voltage - controlled oscillator (vco). ( ) r d ref f in pfd + = 1 (2) where: ref in is the reference input frequen cy. d is the ref in doubler bit. r is the preset divide ratio of binary 4 - bit programmable reference counter (1 to 15). int is the preset divide ratio of binary 9 - bit counter (31 to 511). mod is the preset modulus ratio of binary 12 - bit program - mable frac c ounter (2 to 4095). frac is the preset fractional ratio of binary 12 - bit programmable frac counter (0 to mod - 1). r - counter the 4 - bit r - counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. divisi on ratios from 1 to 15 are allowed. phase frequency dete ctor (pfd) and charge pump the pfd takes inputs from the r - counter and n - counter and produces an output proportional to the phase and frequency difference between them. figur e 17 is a simplified schematic. the pfd includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. u3 clr2 q2 d2 u2 down up hi hi cp ?in +in charge pum p del a y clr1 q1 d1 u1 04833-017 figure 17 . pfd simplified schematic
adf4154 data sheet rev. c | page 10 of 24 muxout and lock dete ct the output multiplexer on the adf4154 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (see table 8 ). figure 18 shows the muxout section in block diagram form. the n - channel, open - drain, analog lock detect should be operated with an external pull - up resi stor of 10 k? nominal. when lock has been detected, the lock detect is high with narrow low - going pulses. r-divider output n-divider output analog lock detect dgnd contro l mux muxout dv dd logic low f as t -lock contro l three-s ta te output digi t al lock detect 04833-018 logic high figure 18 . muxout schematic input shift register s the adf4154 dig ital section includes a 4 - bit r value , a 9 - bit rf n value , a 12 - bit rf frac value , and a 12 - bit interpolator modulus value/fast - lock timer . data is clocked msb first into the 24 - bit shift register on each rising edge of clk. data is transferred from the shift register to one of four latches on the rising edge o f le. the destination latch is determined by the state of the two control bits (c2 and c1) in the shift register. the se are the two lsbs , db1 and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . table 6 shows a summary of how the latches are programmed. program modes table 5 through table 9 show how to set up the program modes in the adf4154. t he adf4154 programmable modulus is double buffered , meaning that two events must occur before the part can use a new modulus value. the f irst event is that the new modulus value must be latched into the device by writing to the r - divider register , and the s econd event is that a new write must be performed on the n - di vider register. therefore, when ever the modulus value is updated, the n - divider register must be written to so that the modulus value is loaded correctly. table 5 . c2 and c1 truth table control bits c2 c1 data latch 0 0 n - divider register 0 1 r - divider register 1 0 control register 1 1 noise and spur register
data sheet adf4154 rev. c | page 11 of 24 registers table 6 . register summary noise and spur reg db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 noise and spur mode db2 t9 noise and spur mode rese r ved n-divider reg db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f1 1 f12 n1 n3 n4 n5 n6 control bits control bits control bits control bits 12-bit rf frac v alue db23 db22 db21 n7 n8 n9 9-bit rf n v alue n2 f as t -lock fl1 r-divider reg db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m1 1 m12 r1 r3 r4 12-bit interpol a t or modulus v alue/ f as t -lock timer 4-bit r v alue r2 muxout p2 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load contro l rese r ved rese r ved prescaler contro l reg ref in doubler db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 0 0 0 0 charge pump current setting phase detector polarity rese r ved lock detect precision rf power- down rf charge pump three-state rf counter reset db15 cp3 cp/2 04833-019
adf4154 data sheet rev. c | page 12 of 24 table 7. n - divider register map f12 0 0 0 0 . . . 1 1 1 1 f1 1 0 0 0 0 . . . 1 1 1 1 f10 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... f3 0 0 0 0 . . . 1 1 1 1 f2 0 0 1 1 . . . 0 0 1 1 f1 0 1 0 1 . . . 0 1 0 1 fractiona l v alue (frac) 0 1 2 3 . . . 4092 4093 4094 4095 n9 0 0 0 0 . . . 1 1 1 n8 0 0 0 0 . . . 1 1 1 n7 0 0 0 0 . . . 1 1 1 n6 0 1 1 1 . . . 1 1 1 n5 1 0 0 0 . . . 1 1 1 n4 1 0 0 0 . . . 1 1 1 n3 1 0 0 0 . . . 1 1 1 n2 1 0 0 1 . . . 0 1 1 n1 1 0 1 0 . . . 1 0 1 integer v alue (int) 31 32 33 34 . . . 509 510 51 1 fl1 0 1 f as t -lock norma l oper a tion f as t -lock enabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f1 1 f12 n1 n3 n4 n5 n6 contro l bits 12-bit frac v alue (frac) db23 db22 db21 n7 n8 n9 9-bit rf n v alue (int) n2 f as t -lock fl1 04833-020
data sheet adf4154 rev. c | page 13 of 24 table 8. r - divider register map 04833-021 m12 interpol a t or modulus v alue (mod) m1 1 m10 m3 m2 m1 0 0 .......... 0 1 0 2 0 0 .......... 0 1 1 3 0 0 .......... 1 0 0 4 . . .......... . . . . . . .......... . . . . . . .......... . . . . 1 1 .......... 1 0 0 4092 1 1 .......... 1 0 1 4093 1 1 .......... 1 1 0 4094 1 0 0 0 . . . 1 1 1 1 1 .......... 1 1 1 4095 r v alue divide r a tio r4 r3 r2 r1 0 0 0 0 . . . 1 12 1 13 1 14 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 1 2 3 4 . . . 0 1 0 1 15 p1 prescaler 0 4/5 1 8/9 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m1 1 m12 r1 r3 r4 contro l bits 12-bit interpolator modulus value (mod)/ fast-lock timer 4-bit r v alue r2 muxout 0 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load contro l rese r ved prescaler p3 load contro l 0 norma l oper a tion 1 load f ast lock timer m3 m2 m1 muxout 0 three-s ta te output digi t al lock detect analog lock detect 0 0 n divider output logic high logic low 0 1 r divider output 1 1 f astlock switch 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
adf4154 data sheet rev. c | page 14 of 24 table 9 . control register map 04833-022 u3 rf power-down 0 norma l oper a tion 1 power-down u4 lock detect precision 0 1 24 pfd cycles 40 pfd cycles i cp (ma) cp3 cp2 cp1 cp0 2.7k? 5.1k? 10k? 0 1.18 0.63 0.32 0 2.46 1.25 0.64 0 3.54 1.88 0.96 0 4.72 2.50 1.28 0 5.9 3.13 1.59 0 7.08 3.75 1.92 0 8.26 4.38 2.23 0 9.45 5.00 2.55 1 0.59 0.31 0.16 1 1.23 0.63 0.32 1 1.77 0.94 0.48 1 2.36 1.25 0.64 1 2.95 1.57 0.8 1 3.54 1.88 0.96 1 4.13 2.19 1.12 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4.73 2.50 1.28 u5 phase detec t or polarit y 0 neg a tive 1 positive u2 rf charge pum p three-s ta te 0 disabled 1 three-s ta te u1 counter reset 0 disabled enabled 1 ref in doubler u6 0 disabled enabled 1 ref in doubler db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 s1 s2 s3 s4 contro l bits charge pump current setting phase detector polarity resync lock detect precision rf power- down rf charge pump three-state rf counter reset db15 cp3 cp/2 s4 s3 s2 s1 resync 0 1 1 0 0 2 0 1 3 . . . . . . . . . 1 1 13 1 0 14 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 15
data sheet adf4154 rev. c | page 15 of 24 table 10 . noise and spur register 04833-023 db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 contro l bits noise and spur mode db2 t9 noise and spur mode rese r ved rese r ved rese r ved rese r ved db10, db5, db4, db3 0 noise and spur setting lowest spur mode low noise and spur mode lowest noise mode db9, db8, db7, db6, db2 00000 11 100 1111 1 these bits must be set to 0 for normal operation.
adf4154 data sheet rev. c | page 16 of 24 register definition s n - divider register, r0 th e on - chip n - divider register is programmed by setting r0 [1, 0] to [0, 0]. tabl e 7 shows the input data format for programming this register. 9 - bit rf n value (int) these nine bits control what is loaded as the int value. this is used to determine the overall feedback division factor (see equation 1). 12- bit rf frac value these 12 bits control what is loaded as the frac value into the fractional interpolator. this value helps determine the overall feedback division factor (see equ ation 1). the frac value must be less than the value loaded into the mod register. fast lock setting the part to logic high enables fast - lock mode. to use fast lock , the required time value for wide bandwidth mode must be loaded into the r - divider register . the charge pump current increases from 16 the minimum current and reverts back to 1 the minimum current after the time value loaded expires . see the fast - lock timer and register sequences section for more information. r - divi der register, r1 the on - chip r - divider register is programmed by setting r1 [1, 0] to [0, 1]. tabl e 8 shows the input data format for programming this register. load control when this bit is set to logic high, the value being pr ogrammed in the modulus is not loaded into the modulus. instead, it sets the fast - lock timer. the value of the fast - lock timer divided by f pfd is the amount of time the pll stays in wide bandwidth mode. muxout the on - chip multiplexer is controlled by r1 [2 2 ... 20] on the adf4154. table 8 shows the truth table. digital lock detect the digital lock detect output goes high if there are 40 successive pfd cycles with an input error of less than 15 ns. it stays high until a new channel is programmed or until the error at the pfd input exceeds 30 ns for one or more cycles. if the loop bandwidth is narrow compared with the pfd frequency, the error at the pfd inputs may drop below 15 ns for 40 cycles around a cycle slip. therefore, the dig ital lock detect may briefly, and falsely , go high until the error exceeds 30 ns. in this case, the digital lock detect is reliable only as a loss - of - lock detector. prescaler (p/p + 1) the dual - modulus prescaler (p/p + 1), along with the int, frac, and mo d counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, the prescaler uses the clock from the rf input stage and divides it down for the counters. the prescaler is based on a synchronous 4/5 core. when it is set to 4/5, the maximum rf frequency allowed is 2 ghz. therefore, when operating the adf4154 with frequencies greater than 2 ghz, the prescaler must be set to 8/9. the prescaler limits the int value as follows: with p = 4/5, n min = 31 with p = 8/9, n min = 91 the prescaler can also influence the phase noise performance. if int < 91, a prescaler of 4/5 should be used. for applications where int > 91, a prescaler of 8/9 should be used for optimum noise performance (see tabl e 8 ). 4 - bit r value the 4 - bit r value allows the input reference frequency (ref in ) to be divided down to produce the reference clock for the pfd . division ratios from 1 to 15 are allowed. 12- bit interpolator modulus value /fast - lock timer depending on the value o f the load control bit, bits db13 : db2 can either be used to set the modulus or the fast - lock timer value . when the load control bit (db23) is set to 0, the required modulus can be programmed in the r - divider register (db13 : db2). when the load control bit (db23) is set to 1, the required fast - lock timer value can be programmed in the r - divider register (db13 : db2). this programmable register sets the fractional modulus, which is the ratio of the pfd frequency to the channel step resolution on the rf output. refer to the rf synthesizer: a worked example section for more information. the adf4154 programmable modulus is double buffered , meaning that two events must occur before the part can use a new modulus value. the first event is that the new modulus value must be latched into the device by writing to the r - divider register , and the s econd event is that a new write must be performed on the n - di vider register. therefore, when ever the modulus value is updated, the n - divider register must be written to so that the modulus value is loaded correctly. control register, r2 the on - chip control register is programmed by setting r2 [1, 0] to [0, 1]. table 9 shows the input data format for programming this register . rf counter reset db2 is the rf counter reset bit for the adf4154. when this bit is set to 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be set to 0.
data sheet adf4154 rev. c | page 17 of 24 rf charge pump three - state this bit (db3) puts the charge pump into three - state mode when it is programmed to 1. for normal operation, i t should be set to 0. rf power - down db4 on the adf4154 provides the programmable power - down mode. setting bit db4 to 1 powers down the device. setting bit db4 to 0 returns the synthes izer to normal operation. while in software power - down mode, the part retains all information in its registers. only when supplies are removed are the register contents lost. when a power - down is activated, the following events occur: 1. all active dc curr ent paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three - state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input is de biased. 6. the input register remains a ctive and capable of loading and latching data. lock detect precision (ldp) when the ldp bit (db5) is programmed to 0, 24 consecutive reference cycles of 15 ns must occur before the digital lock detect is set. when this bit is programmed to 1, 40 consecuti ve reference cycles of 15 ns must occur before digital lock detect is set. phase detector polarity db6 sets the phase detector polarity. when the vco characteristics are positive, this bit should be set to 1. when they are negative, this bit should be set to 0. charge pump (cp) current setting and cp/2 db7, db8, db9, and db10 set the charge pump current, which should be set according to the loop filter design (see table 9 ). ref in doubler setting the ref in doubler bit (db11) to 0 f eeds the ref in signal directly to the 4 - bit r - counter, which disables the doubler. setting the ref in doubler bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 4 - bit r - counter. when the doubler is disabled, the ref in falling e dge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chosen, the in - ban d phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mode and in the lowest noise and spur mode. the phase noise is insensitive to the ref in duty cycle when the doubler is disabled. the maximum allowed ref in frequency when the doubler is enabled is 30 mhz. noise and spur regis ter, r3 the on - chip noise and spur register is programmed by setting r3 [1, 0] to [1, 1]. table 10 shows the input data format for programming this register. noise and spur mode noise and spur mode allows the user to optimize a design either for improved spurious performa nce or for improved phase noise performance. when the lowest spur setting is chosen, dither is enabled. this randomizes the fractional quantization noise so that it looks more like white noise than spurious noise , meaning that the part is optimized for imp roved spurious performance. this operation is typically used when the pll closed - loop band - width is wide for fast - locking applications. a wide - loop bandwidth is defined as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res ). a wi de - loop filter does not attenuate the spurs to a level that a narrow - loop bandwidth would. when the low noise and spur setting is enabled, dither is disabled. this optimizes the synthesizer to operate with improved noise performance. however, the spurious performance is degraded in this m ode compared with the lowest spur setting. to further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. as well as disabling the dither, it ensures that the charge pump o perates in an optimum region for noise performance. this setting is extremely useful if a narrow - loop filter bandwidth is used. the synthesizer ensures extremely low noise , and the filter attenuates the spurs. the typical performance characteristics show t he trade - off s in a typical wcdma setup for different noise and spur settings. reserved bits these bits should be set to 0 for normal operation.
adf4154 data sheet rev. c | page 18 of 24 initialization seque nce the following initialization sequence should be followed after powering up the part: 1. cl ear all test modes by writing all 0 s to the noise and spur register. 2. select the noise and spur mode required for the application by writing to the noise and spur register. for example, writing hex 0003c7 to the part selects low noise mode. 3. enable the coun ter reset in the control register by writing a 1 to db2 and select ing the required settings in the control register. 4. load the r - divider register (with the load control bit [db23] set to 0). 5. load the n - divider register. 6. disable the counter reset by writing a 0 to db2 in the control register. the part should now lock to the set frequency. rf synthesizer: a wo rked example this equation governs how the synthesizer should be programmed. rf out = [ int + ( frac/ mod )] [ f pfd ] (3) where: rf out is the rf frequency ou tput. int is the integer division factor. frac is the fractionality. mod is the modulus. the pfd frequency can be calculated as follows: f pfd = [ ref in (1 = d)/r ] (4) where: ref in is the reference frequency input. d is the value of the rf ref in doubler bi t. r is the rf reference division factor. for example, in a gsm 1800 system, where a 1.8 ghz rf frequency output (rf out ) is required, a 13 mhz reference frequency input (ref in ) is available and a 200 khz channel resolution (f res ) is required on the rf outp ut. res in f ref mod / = 65 khz 200 mhz/ 13 = = mod from equation 4, f pfd = [13 mhz (1 + 0)/1] = 13 mhz (5) ( ) 65 frac int mhz 13 ghz 8 . 1 + = (6) where: int is 138. frac is 30. modulus the choice of modulus (mod) depends on the reference signal (ref in ) available a nd the channel resolution (f res ) required at the rf output. for example, a gsm 1800 system using a 13 mhz ref in set s the modulus to 65, re sulting in meeting the required rf output resolu tion (f res ) of 200 khz (13 mhz/65). reference doubler an d reference di vider the on - chip reference doubler allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency , which in turn improves the no ise performance of the system. for example, d oubling the pfd frequency usually res ults in an improvement in noise performance of 3 db. it is important to note that the pfd cannot operate with frequencies greater than 32 mhz due to a limi tation in the speed of the - circuit of the n - divider. 12- bit programmable mod ulus unlike most fractional - n plls, the adf4154 allows the user to program the modulus over a 12 - bit range. therefore, several configurations of the adf4154 are possible for a n application b y varying the modulus value, the reference doubler , and the 4 - bit r - counter. for example, consider an application that requires a 1.75 ghz rf and a 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible se tup is feeding the 13 mhz ref in directly in to the pfd and programming the modulus to divide by 65, which result s in the required 200 khz resolution. another possible setup is using the reference doubler to create a 26 mhz input frequency from the 13 mhz re f in signal. the 26 mhz signal is then fed into the pfd, which programs the modulus to divide by 130. this setup also results in 200 khz resolution , plus it offers superior phase noise performance compared with the previous setup. the programmable modulus i s also very useful for multi - standard applications. if a dual - mode phone requires pdc and gsm 1800 standards, the programmable modulus is a huge benefit. the pdc requires a 25 khz channel step resolution, whereas the gsm 1800 requires a 200 khz channel ste p resolution. a 13 mhz reference signal could be fed directly to the pfd. the modulus would be programmed to 520 when in pdc mode (13 mhz/520 = 25 khz). the modulus would be reprogrammed to 65 for gsm 1800 operation (13 mhz/65 = 200 khz). it is important t hat the pfd frequency remains con - stant (13 mhz). by keeping the pfd constant, the user can design a one - loop filter that can be used in both setups without running into stability issues. the ratio of the rf frequency to the pfd frequency affects the loop design. by keeping this relationship constant, the same loop filter can be used in both applications. spurious optimizatio n and fast l ock the adf4154 can be optimized for low spurious signals by using the noise and spur register. however, to achieve fast - l ock time, a wider loop bandwidth is needed. note that a wider loop
data sheet adf4154 rev. c | page 19 of 24 bandwidth can lead to notable spurious signals, which cannot be reduced significantly by the loop filter. using the fast - lock feature can achieve the same fast - lock time as the noise and sp ur register, but with the advantage of lower spurious signals because the final loop bandwidth is reduced by a quarter. fast - lock timer and regis ter sequences if the fast - lock mode is used, a timer value needs to be loaded into the pll to determine the ti me spent in wide bandwidth mode . when the load control bit is set to 1, the timer value is loaded via the 12 - bit modulus value. to use fast lock, the pll must be written to in the following sequence: 1. load the r - divider register with db23 = 1 and the chose n fast - lock timer value (db13 to db2) instead of the modulus. note that the duration that the pll remains in wide bandwidth is equal to the fast - lock timer/ f pfd . 2. load the noise and spur register. 3. load the control register. 4. load the r - divider register with db23 = 0 and muxout = 110 (db22 to db20). this sets the fast - lock switch to appear at the muxout pin. all the other needed parameters, including the modulus, also need to be loaded. 5. load the n - divider register, including fast lock = 1 (db23), to activate fast - lock mode. after this procedure is complete , the user need only repeat step 5 to invoke fast lock for subsequent frequency jumps. fast lock: a n example if a pll has reference frequencies of 13 mhz and f pfd = 13 mhz and a required lock time of 50 s, t he pll is set to wide bandwidth for 40 s. if the time period set for the wide bandwidth is 40 s, then fast - lock timer value = time in wide bandwidth f pfd fast - lock timer value = 40 s 13 mhz = 520 therefore, 520 must be loaded into the r - divider regi ster in step 1 of the sequence described in the fast - lock timer and register sequences section. fast lock: loop filter to pology to u s e fa st - lock mode, an extra connection from the pll to the loop filter is needed. the damping res istor in the loop filter must be reduced to ? of its value while in wide bandwidth mode. this is required because the charge pump current is increased by 16 while in wide bandwidth mode , and stability must be ensured. during fast lock , the muxout pin is sh orted to ground ( the fast - lock switch must be programmed to appear at the muxout pin ). the following two topologies can be used: ? divide the damping resistor (r1) into two values (r1 and r1a) that have a ratio of 1:3 (see figure 19). ? connect an extra resistor (r1a) directly from muxout, as shown in figure 19 . the extra resistor must be chosen such that the parallel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the origi nal value of r1 (see figure 20). adf4154 cp muxout c1 c2 r2 r1 r1 a c3 vco 04833-029 figure 19 . fast - l ock loop filter topology topology 1 adf4154 cp muxout c1 c2 r2 r1 r1 a c3 vco 04833-030 figure 20 . fast - l ock loop filter topology topology 2 spur mechanisms the following secti on describes three spur mechanisms that can arise when using a fractional - n synthesizer and how to minimize them in the adf4154. fractional spurs the fractional interpolator in the adf4154 is a third - order - modulator (sdm) with a modulus mod that is programmable to an integer value between 2 and 4 095. in low spur mode (dither enabled), the minimum allowed value of mod is 50. the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. in low noise mode and low noise and spur mode (dither off), the quantization noise from the - modulator appears as frac - tional spurs. the interval between spurs is f pfd /l, where l i s the repeat length of the code sequence in the digital - modulator. for the third - order modulator used in the adf4154, the repeat length depends on the value of mod, as shown in table 11. table 11 . fra ctional spurs with dither off condition (dither off) repeat length spur interval if mod is divisible by 2, but not 3 2 mod channel step/2 if mod is divisible by 3, but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 othe rwise mod channel step
adf4154 data sheet rev. c | page 20 of 24 in low spur mode (dither enabled), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum appear as broadband noise. this can degrade the in - band phase noise at the p ll output by as much as 10 db. therefore, for lowest noise, dither off is a better choice, particularly when the final loop bw is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional sp ur creation are interactions between the rf vco frequency and the reference frequency. when these frequencies are not integer related ( as is the case with fractional - n synthesizer s ), spur sidebands appear on the vco output spectrum at an offset frequency t hat corresponds to the beat note or the difference in frequency between an integer multiple of the reference and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the referen ce , where the difference frequency can be inside the loop bandwidth, thus the name integer boundary spurs. reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwid th. however, any reference feedthrough mechanism that bypasses the loop can cause a problem. one such mechanism is feedthrough of low levels of on - chip reference switching noise through the rf in pin back to the vco, resulting in reference spur levels as hi gh as C 90 dbc. care should be taken in the pcb layout to ensure that the vco is well separated from the input reference to avoid a possible feed - through path on the board. spur consistency when jumping from frequency a to frequency b and then back again us ing fractional - n synthesizers, the spur levels often differ each time frequency a is programmed. however, in the adf4154, the spur levels on any particular channel are always consistent. filter design adi sim pll a filter design and analysis program is avai lable to help the user implement the pll design. visit www.analog.com/pll for a free download of the adisimpll software. the software designs, simulates, and analyzes the entire pll frequency and time domain respons e. various passive and active filter architectures are allowed. interfacing the adf 4154 has a simple, spi? - compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) is high, the 22 bits th at have been clocked into the input register on each rising edge of sclk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 s. aduc812 interface figure 21 shows the interface between the adf4154 and the aduc812 mi croconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051 - based microcontroller. the microconverter is set up for spi master mode with cpha set to 0. to initiate the operation, bring the i / o port driving le low. each latch of the adf4154 requires a 24- bit word, which is accomplished by writing three 8 - bit bytes from the microconverter to the device. after the third byte is written, the le input should be brought high to complete the transfer. when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 180 khz. aduc812 adf4154 sclock sclk sd at a le muxout (lock detect) mosi i/o ports 04833-024 figure 21 . aduc812 - to - adf4154 interface adsp - 21xx interface figure 22 shows the interface between the adf4154 and the adsp - 21xx digital signal processor. as discussed previously, the adf4154 requires a 24 - bit serial word for each latch write. the easiest way to accomplish this using a device in the ad sp - 21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24 - bit word. to program each 24 - bit latch, store each of the three 8 - bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer ed transfer. adsp-21xx adf4154 sclock sclk sd at a le muxout (lock detect) dt tfs i/o flags 04833-025 figure 22 . adsp - 21xx - to - adf4154 interface
data sheet adf4154 rev. c | page 21 of 24 pcb design guideline s for chip scale package the lands on the chip scale package (cp - 20- 1 ) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at l east as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to avoid shorting. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via ba rrel should be plated with 1 oz of copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
adf4154 data sheet rev. c | page 22 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 23 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant t o jedec stand ards mo-220-wggd-1. b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplan arity 0.08 pin 1 indic a t or 2.30 2.10 sq 2.00 for proper connection of the expos ed pad, refer to the pin configuration and functi on descr ipti ons section of this data sheet. 1 2 0 6 1 0 1 1 1 5 1 6 5 08-16- 2010-b figure 24 . 20 - lead lead frame chip scale package [lfcsp _ w q ] 4 mm 4 mm very very thin quad, (cp - 20 - 6 ) dimensions shown in millimeters ordering guide model 1 temperature range description package option adf4154bru ? 40c to +85c 16- lead thin sh rink small outline package [tssop] ru -16 adf4154bru - reel ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4154bru - reel7 ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4154bruz ? 40c to +85c 16- lead th in shrink small outline package [tssop] ru -16 adf4154bruz - rl ? 40c to +85c 16 - lead thin shrink small outline package [tssop] ru - 16 adf4154bruz - rl7 ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4154bcpz ? 40c to +85c 20- lead lead frame chip scale package [lfcsp _w q ] cp -20-6 adf4154bcpz -rl ? 40c to +85c 20- lead lead frame chip scale package [lfcsp _w q ] cp -20-6 adf4154bcpz - rl7 ? 40c to +85c 20- lead lead frame chip scale package [lfcsp _w q ] cp -20-6 eval - adf4154eb z 1 evaluation board 1 z = rohs compliant part.
data sheet adf4154 rev. c | page 23 of 24 notes
adf4154 data sheet rev. c | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04833 - 0 - 8/12(c)

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